Technical Program

 

 

Tuesday 11/03/15  

Time

Event

9:00am    -  10:00am

Registration

10:00am  -  10:30am

Conference Opening - Gunar Schirner (General co-Chair)

10:30am  -  11:00am

Break

11:00am  -  12:30pm

Keynote – Edward Lee, UC Berkeley (USA)

Title: The Internet of Important Things

Session Chair: Achim Rettberg

12:30pm  -  2:00pm

Lunch

2:00pm    -  4:00pm

Session 1: Cyber-Physical Systems

Session Chair: Carlos Eduardo Pereira

4:00pm    -  4:30pm

Break

4:30pm    -  6:00pm

Future Faculty Mentoring (FFM)

Session Chair: Marcelo Götz

6:00pm    -  7:00pm

Panel with Paul Zimmerman (Intel) – Computer Engineering Education (SBESC)

Session chair from SBESC

7:30pm    -  9:00pm

Cocktail and posters (IESS + SBESC)


 

Wednesday 11/04/15

 

Time

Event

9:00am     -  10:30am

Session 4: Memory System Design

Session Chair: Guilherme Bontorin

10:30am   - 11:00am

Break

11:00am   - 12:30pm

Keynote – Björn B. Brandenburg, Max Planck Institute for Software Systems (Germany)

Title: Quo vadis, RTOS? A look at the design of present and future real-time operating systems for the multicore age

Session Chair: Session chair from SBESC

12:30pm   - 2:00pm

Lunch

2:00pm     -  3:30pm

Session 2: System-Level Design

Session Chair: Marco A. Wehrmeister

3:30pm     -  4:30pm

Break

4:30pm     -  6:00pm

Session 3: Multi/Many-Core Systems Design          

Session Chair: TBD

7:00pm     -  9:30pm

Conference Dinner

 

Thursday 11/05/15

Time

Event

9:00am    -  10:30am

Invited Talk - Edelweis Ritt
Session Chair: Achim Rettberg

10:30am  - 11:00am

Break

11:00am  - 12:30pm

Keynote – Mary Backer, HP Labs (USA)

Title: TBD

Session Chair from SBESC

12:30pm  - 2:00pm

Lunch

2:00pm    -  3:30pm

Session 5: Embedded HW/SW Design and Applications

Session Chair: Flávio Wagner

3:30pm    -  4:30pm

Break

4:30pm    -  6:00pm

Closing Session - Marcelo Götz (General co-Chair)

Friday 11/06/15 – Parallel Activities: IESS Social Event and SBESC keynote (shared with IESS)

 

Time

Event

8:00am -aprox.15:00pm

IESS Social Event - Visit of the waterfalls “Iguaçu Falls”

11:00am  - 12:30pm

Keynote – Rajesh Gupta, UC San Diego (USA)

Title: Sense & Adapt: our evolving models of computing machines up and down the abstract stack

Session Chair from SBESC

 

Keynote

 

Edward Lee: The Internet of Important Things

 

Tuesday – 11/03/2015 – 11:00am - 12:30pm

 

Abstract:

 

Cyber-physical systems are integrations of computation, communication networks, and physical dynamics. Applications include manufacturing, transportation, energy production and distribution, biomedical, smart buildings, and military systems, to name a few. Increasingly, today, such systems leverage Internet technology, despite a significant mismatch in technical objectives. A major challenge today is to make this technology reliable, predictable, and controllable enough for "important" things, such as safety-critical and mission-critical systems. The dominant concerns with Web and Cloud technology are scalability, robustness, and reasonable response times.  When physical processes are involved, however, timeliness becomes less of a performance metric, and more of a correctness criterion, and safety becomes a central concern. In this talk, I argue that the engineering models predominantly used for software, and particularly for distributed software, are not well suited to the CPS context. I will examine an alternative view of the CPS design problem that focuses on deterministic models for distributed cyber-physical systems.

See "Keynote" for more details about the speaker!

 

Björn B. Brandenburg: Quo vadis, RTOS? A Look at the Design of Present and Future Real-Time Operating Systems for the Multicore Age

 

Wednesday – 11/04/2015 – 11:00am - 12:30pm

 

Abstract:

 

With the advent of the multicore age, real-time operating system (RTOS) developers are faced with the challenge of having to fundamentally rethink the design of their systems. How to "best" schedule the (increasingly many) available cores? How to enable efficient inter-core synchronization? What about tradeoffs in predictability, flexibility, and performance? More often than not, the "best practices" and design choices made in uniprocessor systems (and codified in RTOS standards) are ill-suited for multicore platforms. In response, the real-time literature has accumulated a bewildering array of new potential solutions — including numerous proposals for global, clustered, partitioned, and semi-partitioned scheduling approaches and various suspension- and spin-based locking protocols, to name just a few categories. However, the right choice in practice is often far from obvious, owing both to the intricate interplay of analytical and engineering concerns in a typical RTOS, and to a not insignificant gap between theory and practice in the real-time literature. Fortunately, research in the past decade has illuminated many of these issues and a clearer picture has emerged. In this talk, based on our experience building LITMUS^RT, I will first illustrate some of the major differences between theory and practice and their implications, and then survey and summarize some of the key results and observations that inform the current state of the art in multiprocessor RTOS design. Finally, I will highlight some of the most pressing open problems and shortcomings in current systems, and speculate on likely trends in the next decade of RTOS research.

 

See "Keynote" for more details about the speaker!

 

Mary Backer: Stepping Stones to an Easier World

 

Thursday – 11/05/2015 – 11:00am - 12:30pm

 

Abstract:

 

New technology brings us many wonders and also many frustrations and obstacles. In this talk I describe two mobile and wearable research projects that attempt to remove some of these obstacles in our daily lives. The first project, Mobius, tackles frustrations around authentication. Every day we must prove our right to access online sites and services, devices such as smart phones and PCs, and physical objects and infrastructure such as cars and doors. We performed a wearable digital diary study to gather information about people's authentication behavior, their likes and dislikes, and what does or doesn't work for them. Results indicate the feasibility of reducing the user authentication burden with a "universal authenticator'' — a wearable device that assumes the responsibility of authenticating its owner to restricted resources, both physical and virtual. Mobius is our prototype design of a universal authenticator in the form of a perpetually powered ring. The second project, the Sound of Silence, makes it easier to share content among and otherwise communicate with participants in an event like a formal meeting, a chance encounter, or a broadcast TV or radio program. We compare simple privacy-preserving "silence signatures" gathered on mobile devices to capture the dynamically changing group membership of such events. For both of these projects I'll describe what worked, what failed, and what we should worry about in the future.

 

See "Keynote" for more details about the speaker!

 

Rajesh Gupta: Sense & Adapt: Our Evolving Models of Computing Machines up and down the Abstract Stack

 

Friday – 11/06/2015 – 11:00am - 12:30pm

 

Remark: This is a keynote from SBESC'15 and occurs after IESS, however, IESS participants are allowed to attend this keynote.

 

Abstract:

 

A modern computing system is an elaborate stack of hardware and software with stable intermediate points that enable a platform builder to construct all sorts of machines with 'commodity' hardware and software pieces. Unfortunately, this extraordinary flexibility comes at a huge cost: two to three orders of magnitude in efficiency and cost. This is far beyond the range of most engineered systems. This observation has been at the root of our quest for new architectures — from modifications to von Neumann to data-flow variants — and new ways of building/synthesizing hardware pieces for new machines — co-processors to synthesized accelerators. This talk pulls the most interesting and promising vectors of research in this line of thinking to outline a vision of emerging machines: that are engineered less but enabled more to sense and adapt the computation to the environment in which they are placed.

 

See "Keynote" for more details about the speaker!

 

Invited Talk

Edelweis Ritt: Embedded Systems in the Brazilian Smart Cities

 

Thursday – 11/05/2015 – 09:00am - 10:30am

 

Abstract:

Smart cities are generally seen as the gateway for sustainable urbanization. While concepts reach from intelligent instrumentation to electronic participation, they all have in common a tremendous potential to improve the efficiency of city management as well as the quality of urban living. The internet of things (IoT) embedded systems are key elements in the design of smart city solutions. Their interoperability and opportunities as an open platform will largely affect the rate of innovation and their availability will accelerate the transformation towards intelligent services. For South America, the topic smart city not only matters because of its high degree of urbanization but also because of the high affinity of its population for networked solutions. This panel will discuss the potential of embedded systems for smart cities In Brazil in the near future and the role Unitec.

 

 See "Keynote" for more details about the speaker!

 

Technical Sessions

 

Session 1: Cyber-Physical Systems

 Session Chair: Carlos Eduardo Pereira

2:00pm – 2:30pm

24R

Ontological User Modeling for Ambient Assisted Living Service Personalization
Mauricio F. de Vargas and Carlos E. Pereira

2:30pm – 3:00pm

25R

Multi-Agent Based Implementation of an Embedded Image Processing System in FPGA for Precision Agriculture using UAVs
Érico Nunes, Lucas Behnck and Carlos Eduardo Pereira

3:00pm – 3:15pm

03S

Combining Service-oriented Computing with Embedded Systems - A Robotics Case Study
Alexander Jungmann, Jan Jatzkowski and Bernd Kleinjohann

3:15pm – 3:30pm

23S

Integration of Robot Operating System and Ptolemy for Design of Real-time Multi-Robots Environments
Luis Feliphe Silva Costa, Alisson Vasconcelos Brito, Tiago Nascimento and Thiago Henrique Menezes Bezerra

 

Session 2: System-Level Design

 Session Chair: Marco A. Wehrmeister

2:00pm – 2:30pm

17R

Bit-Precise Formal Verification for SystemC using Satisfiability Modulo Theories Solving
Lydia Jaß and Paula Herber

2:30pm – 3:00pm

12R

Timed Path Conditions in MATLAB/Simulink
Marcus Mikulcak, Paula Herber, Thomas Göthel and Sabine Glesner

3:00pm – 3:15pm

26S

Structural Contracts – Motivating Contracts to Ensure Extra-Functional Semantics
Gregor Nitsche, Ralph Goergen, Kim Gruettner and Wolfgang Nebel

3:15pm – 3:45pm

19R

Combining an Iterative State-based Timing Analysis wih a Refinement Checking Technique
Tayfun Gezgin, Björn Koopmann and Achim Rettberg

 

Session 3: Multi/Many-Core System Design

 Session Chair: TBD

4:30pm – 5:00pm

02R

Hierarchical Multicore-Scheduling for Virtualization of Dependent Real-Time Systems
Jan Jatzkowski, Marcio Kreutz and Achim Rettberg

5:00pm – 5:30pm

01R

Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs
Andrés Goens and Jeronimo Castrillon

5:30pm – 6:00pm

15R

Modeling and Analysis of SLDL-captured NoC Abstractions
Ran Hao, Nasibeh Teimouri, Kasra Moazzemi and Gunar Schirner

 

 

 

Session 4: Memory System Design

Session Chair: Guilherme Bontorin

9:00am – 9:30am

18R

Taming the Memory Demand Complexity of Adaptive Vision Algorithms
Majid Sabbagh, Hamed Tabkhi and Gunar Schirner

9:30am – 10:00am

05R

HMC and DDR performance trade-offs
Paulo Santos, Marco Antonio Zanata Alves and Luigi Carro

10:00am– 10:30pm

06S

Managing Cache Memory Resources in Adaptive Many-core Systems
Gustavo Girão and Flavio Wagner

 

Session 5: Embedded HW/SW Design and Applications

 Session Chair: Flávio Wagner

 

2:00pm – 2:30pm

08S

A UML profile to couple the production code generator TargetLink with UML design tools
Malte Falk, Stefan Walter and Achim Rettberg

2:30pm – 3:00pm

16R

Rapid, High-Level Performance Estimation for DSE using Calibrated Weight Tables
Kasra Moazzemi, Smit Patel, Shen Feng and Gunar Schirner

3:00pm – 3:30pm

20R

Low Latency FPGA Implementation of Izhikevich-Neuron Model
Vitor Bandeira, Vivianne Costa, Guilherme Bontorin and Ricardo Reis

3:30pm – 4:00pm

27S

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays
Éricles Sousa, Frank Hannig, and Jürgen Teich